The invention relates to testing parameters of an electronic device.
The electrical properties of semiconductor devices vary from device to device. These variations occur even when semiconductor devices are of the same type and are fabricated on the same wafer. In recognition of these variations, manufacturers of the semiconductor devices typically perform several tests on each device to test various electrical parameters of the device and verify that certain minimum standards are met.
The tests are typically conducted using a tester that furnishes test signals (e.g., address, data and control signals) to the device being tested. The tester generates several internal clock signals that are used to clock the transitions of the test signals. Although the clock signals have the same frequency, the relative phases of the clock signals are adjusted to test different parameters of the device.
For example, to test an address setup time t.sub.AS of a synchronous dynamic random access memory (SDRAM), one of the test signals provided by the tester is a system clock signal that clocks operations of the SDRAM and is synchronized to one of the internal clock signals. The tester also provides a group of different test signals that are indicative of an address in the SDRAM. This group of signals is synchronized to another one of the internal clock signals of the tester and is slightly offset in phase from the system clock signal. Thus, the address setup time tested is represented by the difference in phase between the two internal clock signals.
As a result of this type of testing, the period of the internal clock signals of the tester may be relatively long compared to the time interval tested. However, this type of testing does accommodate the situation where one of the test signals must transition between two states faster than the period of the internal clock signal.
Referring to FIG. 1, as an example, for a memory device (e.g., a SDRAM 12), a test sequence might be used to evaluate how quickly the memory device performs a write operation, i.e., the test sequence evaluates a write recovery time interval t.sub.WR of the device. In this test sequence, a tester 10 interacts with the SDRAM 12 to initiate and control a sequence of write operations. The tester 10 limits the duration of each write operation to a maximum acceptable write recovery time interval. If defective, the SDRAM 12 is not able to store test data (furnished by the tester 10) in its memory cells due to the time limitation imposed by the tester 10. Thus, the tester 10 completes the test by reading values from the memory cells and comparing the test data to the values that are read.
Referring to FIG. 2, the tester 10 typically furnishes a write enable signal WE#, a write command and other signals to control each write operation. The SDRAM 12 begins the write operation at time T.sub.START when the SDRAM 12 latches the write command on a positive edge of a clock signal (called CLK). If the write command is not present on the next positive edge of the CLK signal, then a duration 15 of the write operation is one period of the CLK signal.
As a result of this type of testing, the minimum time interval that may be tested is equal to the period of the clock signal CLK. However, due to nonideal properties (e.g., rise and fall times) of the clock signal CLK, the period of the clock signal CLK typically has to be much smaller than the time interval tested.